Programmable logic devices (PLDs) in which the circuit configuration can be switched, such as field-programmable gate arrays (FPGA), are in wide use (Patent Document 1, for example). The applicant or inventor has developed “memory-based programmable logic devices (MPLD)” (registered trademark) in which a circuit configuration is constituted of memory cell units. MPLDs are disclosed in Patent Document 1 below, for example. In MPLDs, memory arrays referred to as “multiple lookup tables” (MLUTs) are connected to each other. MLUTs store truth table data and form wiring elements and logic elements. MPLDs realize almost the same functions as FPGAs by having these MLUTs arranged in an array and connected to each other.
Also, MPLDs are devices having flexibility in terms of logic regions and wiring regions by using MLUTs both as logic elements and wiring elements by truth table data (Patent Document 2, for example), and differ from FPGAs having specialized switching circuits at the connections between memory cell units.
Additionally, multi-directional type MLUTs (Patent Document 1) having address lines or data lines inputting or outputting in multiple directions, and rectangular type MLUTs (Patent Document 3) that are rectangular and that input and output data in only the horizontal direction are disclosed as types of MLUTs. The connection between MLUTs is achieved by forming a pair including 1 bit each of an address line and a data line, thereby realizing pseudo-bidirectional lines. These pseudo-bidirectional lines are referred to as an “AD pair.” For multi-directional type MLUTs, adjacent MLUTs are connected by one AD pair, and thus, data transmitted between adjacent MLUTs is 1 bit.